1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically, to a metal oxide semiconductor (MOS) transistor having a wide gate width with use of a trench.
2. Description of the Related Art
A MOS transistor is an electronic device at the core of electronic technology, and hence downsizing and driving performance enhancement of the MOS transistor are important issues. As a method of enhancing the driving performance of the MOS transistor, there is given a method involving making a gate width longer, to thereby decrease the on-resistance. However, when the gate width is made longer, there arises a problem in that an occupation area of the MOS transistor becomes larger.
JP 2006-294645 A proposes a technology in which the gate width is made longer while suppressing an increase of the occupation area of the MOS transistor having a lateral MOS structure. In this technology, as illustrated in a perspective view of FIG. 2A, concave portions (trenches) 11a are formed in a well 2, and a gate electrode 3 is formed on convex portions 11b and in the concave portions 11a via a gate insulating film 4. In a surface portion of the well 2, a source region 5a is formed on one side of the gate electrode 3, and a drain region 6a is formed on the other side thereof.
An A-A sectional view and a B-B sectional view of FIG. 2A are illustrated in FIG. 2B and FIG. 2C, respectively. As illustrated in the A-A sectional view, the gate electrode 3 is formed in the concave portions 11a, and hence a length of an outline which is brought into contact with the gate insulating film 4 becomes a gate width. In this way, according to this technology, a length of an effective gate width may be made longer than a length of the gate electrode 3 on a surface of a gate portion by forming the gate portion in a trench structure having the concave portions 11a and the convex portions 11b, whereby an on-resistance per unit area may be reduced without reducing a withstanding voltage of the MOS transistor.
In this technology, as illustrated in the perspective view of FIG. 2A, the trenches are formed in the well 2 to form the concave portions 11a and the convex portions 11b, and the gate electrode 3 is formed on top surfaces of the convex portions 11b and in the concave portions 11a via the gate insulating film 4. In the surface portion of the well 2, the source region 5a is formed on one side of the gate electrode 3, and the drain region 6a is formed on the other side thereof.
FIG. 2B is the A-A sectional view of FIG. 2A, in which a channel region 9 is formed along the concave portions 11a and the convex portions 11b by applying a voltage to the gate electrode 3, and a gate width may be made longer by a length of side surfaces of the concave portions compared with a general MOS transistor in which a trench is not formed, whereby the on-resistance per unit area may be reduced without reducing the withstanding voltage of the MOS transistor.
However, in the structure of FIG. 2A, there arises a problem in that expected driving performance cannot be obtained as the gate length L becomes shorter.
FIG. 2C is the B-B sectional view of FIG. 2A. As apparent from FIG. 2B, FIG. 2C is a sectional view obtained by cutting a portion immediately next to a side wall of the trench, in which the channel region 9 is formed. Current flows via current paths 10 into the channel region 9 formed between the source and the drain, which is illustrated in FIG. 2C. The current path 10 located in an upper portion of the channel region 9 is shorter than the current path 10 located in a lower portion of the channel region 9, and this difference is markedly observed as the gate length L becomes shorter. Specifically, as the gate length L becomes shorter, a current flows through the current path 10 located in the upper portion of the channel region 9 in a concentrated manner. This results in a phenomenon in which a current hardly flows through the current path 10 located in the lower portion. Thus, the channel region 9 cannot be used effectively, and as a result, expected driving performance cannot be obtained. This may be because the source region 5a and the drain region 6a have a depth shallower than that of the trench. When the depth of the source region 5a and the drain region 6a may be made almost equal to the trench depth, the above-mentioned current concentration does not occur even with the shorter gate length L, and current flows uniformly in the entire channel. However, as to the source region and drain region to which a normal impurity implantation is applied, even when the source region and the drain region are deeply formed, it is generally difficult to form them with a depth larger than 0.5 μm.
Through thermal diffusion after the impurity implantation, the impurities can be diffused to a deeper level. However, the diffusion lowers the concentration of the source and drain regions, and causes an increase of a parasitic resistance and deterioration of the driving performance. In addition, the impurities diffuse not only in a depth direction but also in a lateral direction, and hence an effective length L becomes shorter. In order to attain a target effective length L, a length L of a layout has to be made larger by an amount for the lateral-direction diffusion, and as a result, a size of the device increases and the driving performance per unit area deteriorates.
As another method, exceptionally large implantation energy can be used to diffuse the impurities deeper. Similarly to the above-mentioned method, also in this method, lateral-direction diffusion of the impurities deteriorates the driving performance per unit area. Further, the increased implantation energy causes a risk that the impurities penetrate a gate electrode to be implanted into the channel.